Field of the Invention
The present invention relates to an organic light emitting display (OLED) device, and more particularly, to a top emission type OLED device and a method of manufacturing the same.
Discussion of the Related Art
An organic light emitting display (OLED) device is a self-light emitting display device, and has many advantages such as low power consumption, fast response speed, high light emission efficiency, high luminance and wide viewing angle. The OLED device is categorized into a top emission type and a bottom emission type depending on the direction in which the light emitted from an organic light emitting diode is transmitted.
In the bottom emission type OLED device, since a circuit element is disposed between a light emitting layer and an image display surface, the aperture ratio may be lowered due to the circuit element. On the other hand, the top emission type OLED device has a higher aperture ratio, because a circuit element is not disposed between a light emitting layer and an image display surface.
FIG. 1 is a cross-sectional view illustrating a top emission type organic light emitting display device according to the related art.
As illustrated in FIG. 1, a thin film transistor layer T, a passivation layer 20, a first planarization layer 31, a second planarization layer 32, a first anode electrode 40, a second anode electrode 60, a first auxiliary electrode 50, a second auxiliary electrode 70, a bank 80, a partition wall 92, an organic light emitting layer 94, and a cathode electrode 96 are formed in an active area AA on a substrate 10.
The thin film transistor layer T includes an active layer 11, a gate insulating film 12, a gate electrode 13, an interlayer dielectric 14, a source electrode 15, and a drain electrode 16.
The first anode electrode 40 and the first auxiliary electrode 50 are formed on the first planarization layer 31, and the second anode electrode 60 and the second auxiliary electrode 70 are formed on the second planarization layer 32. The first auxiliary electrode 50 serves to reduce the resistance of the cathode electrode 96 together with the second auxiliary electrode 70.
The bank 80 is formed on the second anode electrode 60 and the second auxiliary electrode 70 to define a pixel area, the organic light emitting layer 94 is formed within the pixel area defined by the bank 80, and the cathode electrode 96 is formed on the organic light emitting layer 94.
The partition wall 92 is formed on the second auxiliary electrode 70. The partition wall 92 is spaced apart from the bank 80 at a predetermined distance, and the second auxiliary electrode 70 is connected with the cathode electrode 96 through the spaced area between the partition wall 92 and the bank 80 to reduce the resistance of the cathode electrode 96.
In case of the top emission type, the light emitted from the organic light emitting layer 94 passes through the cathode electrode 96. Therefore, the cathode electrode 96 is typically formed using a transparent conductive material, which increases the resistance of the cathode electrode 96. In order to reduce the resistance of the cathode electrode 96, the cathode electrode 96 is connected with the first auxiliary electrode 50 and the second auxiliary electrode 70.
Particularly, the OLED device illustrated in FIG. 1 includes two auxiliary electrodes of the first auxiliary electrode 50 and the second auxiliary electrode 70, which are connected with each other to reduce the resistance of the cathode electrode 96. In such a case, because the second auxiliary electrode 70 is formed on the same layer as the second anode electrode 60, if a width of the second auxiliary electrode 70 increases to reduce the resistance of the cathode electrode 96, a width of the second anode electrode 60 is desired to be reduced, which may reduce the pixel area. Therefore, there is limitation in increasing the width of the second auxiliary electrode 70.
To address such a problem, the first auxiliary electrode 50 is additionally formed below the second auxiliary electrode 70 to reduce the resistance of the cathode electrode 96, without reducing the pixel area.
The aforementioned top emission type transparent OLED device according to the related art may have the following problems.
An array test is typically performed to determine whether there is any electrical defect in electrodes formed on the substrate 10 in which a test signal is applied to an electrode of each layer and the charge of the second anode electrode 60 is checked through an image in each pixel. Specifically, the transparent OLED device includes a transmissive portion and a light emitting portion, and all the elements of the light emitting portion are vertically deposited, as illustrated in FIG. 1, to obtain an enlarged area of the transmissive portion and improve transmittance.
When an array test is performed for the OLED device in which the thin film transistor layer T, the first anode electrode 40, and the second anode electrode 60 are vertically deposited as illustrated in FIG. 1, if a test signal is applied to the second anode electrode 60 to determine whether there is any defect in the second anode electrode 60 by checking an image in each pixel, the defect of the second anode electrode 60 may not be accurately tested due to interference caused by the thin film transistor layer T and the first anode electrode 60, which are deposited below the second anode electrode 60.
Particularly, since a low potential voltage Vss signal is applied to the first auxiliary electrode 50 formed in the light emitting portion of each pixel, the result of the array test for all pixels is represented by the same image, and thus, it may not be possible to determine whether there is any defect in the second anode electrode 60 of a specific pixel.